1. Field of the Invention
The invention relates to a process that allows in-situ, lower cost processing of fabrication of complementary bipolar (CB)liner RIE and CB oxide RIE using the same high plasma power tool, while simultaneously allowing epitaxial(epi)-regrowth of amorphous Si in DRAM production.
2. The Prior Art
In dynamic random access memory (DRAM) development, doped poly-Si is used as the complementary bipolar (CB) contact as well as the source of doping in the contact region.
A method of manufacturing a MOSFET is disclosed in U.S. Pat. No. 5,824,586. The method comprises:
forming a source region and a drain region in a substrate;
forming a gate oxide region on a surface of the substrate;
forming a gate on the gate oxide region;
forming gate oxide spacers adjacent to the gate and contiguous with the gate oxide region;
depositing undoped amorphous silicon;
ion implanting wherein the source and drain junctions are formed;
a first rapid thermal anneal wherein limited solid phase epitaxial silicon growth takes place in regions of the amorphous silicon with underlying silicon; and
etching the remaining amorphous silicon.
A method for forming thickened source/drain contact regions for FETs is disclosed in U.S. Pat. No. 5,250,454. The method entails:
depositing a layer of amorphous silicon covering the source and drain contact regions, the gate and the side wall spacer;
heating the layer of amorphous silicon to a temperature sufficient to induce epitaxial regrowth of the amorphous silicon layer in the source and drain regions to form thickened source and drain contact regions; and
wet-etching the substrate to remove the uncrystallized portion of the amorphous silicon in the regions where epitaxial regrowth was not induced and to remove at least a portion of the side wall spacer leaving a groove circumscribing the gate.
U.S. Pat. No. 5,980,265 discloses stable, high temperature electrical contacts to silicon carbide formed using a unique silicide formation process that employs a sacrificial silicon layer between the silicon carbide and a contacting metal, which forms a metal silicide interlayer providing the resulting contact with low specific contact resistance and high electrical and structural stability. The contact interface is formed by reaction below the semiconductor surface, thereby making the in-situ silicide formation process insensitive to surface impurities and oxides and permitting the controlled formation of silicides without the formation of excess carbon and carbides at the contact interface. The silicon layer may optionally be doped in situ during growth or implanted with dopants after growth, to lower the contact resistance and enhance its operational stability.
A method of forming a device quality silicon carbide epitaxial film is disclosed in U.S. Pat. No. 6,329,088 B1. The method comprises: depositing the film at sub-atmospheric pressure conditions on a silicon carbide substrate of hexagonal crystal form, off cut towards the  less than 1100 greater than  crystalline direction of the substrate, wherein the silicon carbide epitaxial film has a smooth surface morphology, within an edge exclusion area, and has a root mean square roughness not exceeding about 2 nanometers in a 20xc3x9720 xcexcm2 area.
U.S. Pat. No. 6,107,197 discloses a method of removing a carbon-contaminated layer from a silicon substrate surface for subsequent selective silicon epitaxial growth thereon.
The method comprises:
exposing a carbon-contaminated layer on the silicon substrate surface to a chlorine radical to cause a reaction of the chlorine radical with carbon atoms of the carbon-contaminated layer for removal of the carbon-contaminated layer from the silicon substrate surface, wherein the chlorine radical has been generated by passing a chlorine gas through a heated filament.
R. Basir, et al, in xe2x80x9cA Simple Process to Produce a High Quality Silicon Surface Prior To Selective Epitaxial growthxe2x80x9d, IEEE Electron Device Letters Vol. 16, No. 7, July 1995, disclose a process for eliminating etch damage resulting from oxide etching using RIE on a seed-hole prior to selective epitaxial growth of silicon.
There is a need to provide an in-situ low cost processing means to allow a CB liner RIE and a CB oxide RIE to be conducted in the same high plasma power system while at the same time enabling epi-regrowth of amorphous Si by disrupting the Sixe2x80x94C bonding.
One object of the present invention is to provide an in-situ lower cost processing means to allow a CB liner RIE and a CB oxide RIE to be conducted in the same high plasma power system.
Another object of the present invention is to provide an in-situ lower cost processing means to allow a CB liner RIE and CB oxide RIE to be conducted in the same high plasma power system, and at the same time enable epi-regrowth of amorphous Si.
A further object of the present invention is to provide an in-situ lower cost processing means to allow a CB liner RIE and a CB oxide RIE to be conducted in the same high plasma power system, and at the same time enable epi-regrowth of amorphous Si by disrupting the Sixe2x80x94C bonding.
In general, the invention is accomplished by:
a) affecting a CB reactive ion etch on a substrate to remove SiN and SiO;
b) affecting an O plasma ex-situ clean;
c) affecting a Huang AB clean;
d) affecting a dilute hydrofluoric acid (DHF) clean;
e) depositing amorphous Si; and
f) annealing to recrystallize and regrow amorphous CB
Alternatively, the invention method may be accomplished by:
a) affecting a CB reactive ion etch on a substrate to remove SiN and SiO followed by introducing an O plasma in-situ clean;
b) affecting a Huang AB clean;
c) affecting a dilute hydrofluoric acid (DHF) clean;
d) depositing amorphous Si; and
e) annealing to recrystallize and regrow amorphous CB.